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hynix semiconductor inc. 8-bit single-chip microcontrollers GMS90C3X gms90c5x gms97c5x users manual (ver. 3.1a)
version 3.1a published by mcu application team 2001 hynix semiconductor all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and representatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconduc- tor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
gms90 series oct. 2000 ver 3.1a device naming structure gms90x5x frequency package type blank: 24: 40: 12mhz 24mhz 40mhz blank: pl: q: 40pdip 44plcc 44mqfp rom code serial no. rom size 1: 2: 4: 4k bytes 8k bytes 16k bytes 6: 8: 24k bytes 32k bytes operating voltage c: l: 4.25~5.5v 2.7~3.6v hynix semiconductor mcu -gbxxxxxxx gms97x5x frequency package type blank: h: 12/24(5v),12mhz(3v) 33mhz blank: pl: q: 40pdip 44plcc 44mqfp rom size 1: 2: 4: 4k bytes 8k bytes 16k bytes 6: 8: 24k bytes 32k bytes operating voltage c: l: 4.25~5.5v 2.7~3.6v hynix semiconductor mcu xx x mask rom version otp version 16: 16mhz
gms90 series oct. 2000 ver 3.1a gms90seriesselectionguide operating voltage (v) rom size (bytes) ram size (bytes) device name operating frequency (mhz) mask otp 4.25~5.5 rom-less 128 256 gms90c31 gms90c32 12/24/40 12/24/40 4k 8k 16k 24k 32k - - - - - 128 256 256 256 256 gms90c51 gms90c52 gms90c54 gms90c56 gms90c58 12/24/40 12/24/40 12/24/40 12/24/40 12/24/40 - - - - - - - - - - 4k 4k 8k 8k 16k 16k 24k 24k 32k 32k 128 128 256 256 256 256 256 256 256 256 gms97c51 gms97c51h gms97c52 gms97c52h gms97c54 gms97c54h gms97c56 gms97c56h gms97c58 gms97c58h 12/24 33 12/24 33 12/24 33 12/24 33 12/24 33 2.7~3.6 rom-less 128 256 gms90l31 gms90l32 12/16 12/16 4k 8k 16k 24k 32k - - - - - 128 256 256 256 256 gms90l51 gms90l52 gms90l54 gms90l56 gms90l58 12/16 12/16 12/16 12/16 12/16 - - - - - 4k 8k 16k 24k 32k 128 256 256 256 256 gms97l51 gms97l52 gms97l54 gms97l56 gms97l58 12 12 12 12 12
gms90 series oct. 2000 ver 3.1a 1 gms90c31/51, 97c51 gms90l31/51, 97l51 (low voltage versions) ? fully compatible to standard mcs-51 microcontroller ? wide operating frequency up to 40mhz (for more detail, see gms90 series selection guide) ?4k 8 (ep)rom ?128 8ram ? 64k external program memory space ? 64k external data memory space ? four 8-bit ports ? two 16-bit timers / counters ? usart ? five interrupt sources, two priority levels ? power saving idle and power down mode ? quick pulse programming algorithm (in the otp devices) ? 2-level program memory lock (in the otp devices) ? 2.7volt low voltage version available ? p-dip-40, p-lcc-44, p-mqfp-44 package block diagram ram 128 8 port 0 port 1 port 3 port 2 8-bit usart rom / eprom 4k 8 cpu t0 t1 i/o i/o i/o i/o
gms90 series 2 oct. 2000 ver 3.1a gms90c32/52, 97c52 gms90l32/52, 97l52 (low voltage versions) ? fully compatible to standard mcs-51 microcontroller ? wide operating frequency up to 40mhz (for more detail, see gms90 series selection guide) ?8k 8 (ep)rom ?256 8ram ? 64k external program memory space ? 64k external data memory space ? four 8-bit ports ? three 16-bit timers / counters (timer2 with up/down counter feature) ? usart ? six interrupt sources, two priority levels ? power saving idle and power down mode ? quick pulse programming algorithm (in the otp devices) ? 2-level program memory lock (in the otp devices) ? 2.7volt low voltage version available ? p-dip-40, p-lcc-44, p-mqfp-44 package block diagram ram 256 8 port 0 port 1 port 3 port 2 8-bit usart rom / eprom 8k 8 cpu t0 t1 i/o i/o i/o i/o t2
gms90 series oct. 2000 ver 3.1a 3 gms90c54/56/58, 97c54/56/58 gms90l54/56/58, 97l54/56/58 (low voltage versions) ? fully compatible to standard mcs-51 microcontroller ? wide operating frequency up to 40mhz (for more detail, see gms90 series selection guide) ? 16k/24k/32k bytes (ep)rom ?256 8ram ? 64k external program memory space ? 64k external data memory space ? four 8-bit ports ? three 16-bit timers / counters (timer2 with up/down counter feature) ? usart ? one clock output port ? programmable ale pin enable / disable ? six interrupt sources, two priority levels ? power saving idle and power down mode ? quick pulse programming algorithm (in the otp devices) ? 2-level program memory lock (in the otp devices) ? 2.7volt low voltage version available ? p-dip-40, p-lcc-44, p-mqfp-44 package block diagram ram 256 8 port 0 port 1 port 3 port 2 8-bit usart rom / eprom gms9xx54: 16k 8 cpu t0 t1 i/o i/o i/o i/o t2 gms9xx56: 24k 8 gms9xx58: 32k 8
gms90 series 4 oct. 2000 ver 3.1a pin configuration 44-plcc pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea /v pp n.c.* ale / prog psen p2.7 / a15 p2.6 / a14 p2.5 / a13 p1.5 p1.6 p1.7 reset rxd / p3.0 n.c.* txd / p3.1 int0 /p3.2 int1 /p3.3 t0 / p3.4 t1 / p3.5 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss n.c.* p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 p1.4 p1.3 p1.2 p1.1 / t2ex p1.0 / t2 n.c.* v cc p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 index corner n.c.: do not connect.
gms90 series oct. 2000 ver 3.1a 5 40-pdip pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea /v pp ale / prog psen p2.7 / a15 p2.6 / a14 p2.5 / a13 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 p2.4 / a12 p2.3 / a11 p2.2 / a10 p2.1 / a9 p2.0 / a8 p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 v cc t2ex / p1.1 p1.2 p1.3 p1.4 t2 / p1.0 p1.5 p1.6 p1.7 reset rxd / p3.0 txd / p3.1 int0 /p3.2 int1 /p3.3 t0 / p3.4 t1 / p3.5 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1
gms90 series 6 oct. 2000 ver 3.1a 44-mqfp pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea /v pp n.c.* ale / prog psen p2.7 / a15 p2.6 / a14 p2.5 / a13 p1.5 p1.6 p1.7 reset rxd / p3.0 n.c.* txd / p3.1 int0 /p3.2 int1 /p3.3 t0 / p3.4 t1 / p3.5 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss n.c.* p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 p1.4 p1.3 p1.2 p1.1 / t2ex p1.0 / t2 n.c.* v cc p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 n.c.: do not connect.
gms90 series oct. 2000 ver 3.1a 7 logic symbol xtal1 xtal2 reset port 0 8-bit digital i/o port 1 8-bit digital i/o port 2 8-bit digital i/o port 3 8-bit digital i/o ea /v pp ale/prog psen v cc v ss
gms90 series 8 oct. 2000 ver 3.1a pin definitions and functions symbol pin number input/ output function plcc- 44 pdip- 40 mqfp- 44 p1.0-p1.7 2-9 2 3 2 1-8 1 2 1 40-44, 1-3 40 41 40 i/o port1 port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). pins p1.0 and p1.1 also. port1 also receives the low-order address byte during program memory verification. port1 also serves alternate functions of timer 2. p1.0 / t2 : timer/counter 2 external count input p1.1 / t2ex : timer/counter 2 trigger input in gms9xc54/56/58: p1.0 / t2, clock out : timer/counter 2 external count input, clock out p3.0-p3.7 11, 13-19 10-17 5, 7-13 i/o port 3 port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). port 3 also serves the special features of the 80c51 family, as listed below. 11 13 14 15 16 17 18 19 10 11 12 13 14 15 16 17 5 7 8 9 10 11 12 13 p3.0 / rxd p3.1 / txd p3.2 /int0 p3.3 / int1 p3.4 /t0 p3.5 /t1 p3.6 / wr p3.7 /rd receiver data input (asynchronous) or data input output(synchronous) of serial interface 0 transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 interrupt 0 input/timer 0 gate control interrupt 1 input/timer 1 gate control counter 0 input counter 1 input the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0 xtal2 20 18 14 o xtal2 output of the inverting oscillator amplifier.
gms90 series oct. 2000 ver 3.1a 9 xtal1 21 19 15 i xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits.to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. minimum and maximum high and low times as well as rise fall times specified in the ac characteristics must be observed. p2.0-p2.7 24-31 21-28 18-25 i/o port 2 port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics).port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. psen 32 29 26 o the program store enable the read strobe to external program memory when the device is executing code from the external program memory. psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. reset 10 9 4 i reset a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v cc . symbol pin number input/ output function plcc- 44 pdip- 40 mqfp- 44
gms90 series 10 oct. 2000 ver 3.1a ale / prog 33 30 27 o the address latch enable / program pulse output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog )during eprom programming. in gms9xc54/56/58: if desired, ale operation can be disabled by setting bit 0 of sfr location 8e h . with this bit set, the pin is weakly pulled high. the ale disable feature will be terminated by reset. setting the ale-disable bit has no affect if the microcontroller is in external execution mode. ea /v pp 35 31 29 i external access enable / program supply voltage ea must be external held low to enable the device to fetch code from external program memory locations 0000 h to ffff h .ifea is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. this pin also receives the 12.75v programming supply voltage (v pp )during eprom programming. note; however, that if any of the lock bits are programmed, ea will be internally latched on reset. p0.0-p0.7 36-43 32-39 30-37 i/o port 0 port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification in the gms97x5x. external pull-up resistors are required during program verification. v ss 22 20 16 - circuit ground potential v cc 44 40 38 - supply terminal for all operating modes n.c. 1,12 23,34 -6,17 28,39 - no connection symbol pin number input/ output function plcc- 44 pdip- 40 mqfp- 44
gms90 series oct. 2000 ver 3.1a 11 functional description the gms90 series is fully compatible to the standard 8051 microcontroller family. it is compatible with the general 8051 family. while maintaining all architectural and operational characteristics of the general 8051 family. figure 1 shows a block diagram of the gms90 series figure 1. block diagram of the gms90 series rom/eprom 4k/8k/16k 24k/32k ram 128/256 8 osc & timing cpu timer 0 timer 1 timer 2 interrupt unit serial channel port 0 port 1 port 2 port 3 port 0 8-bit digit. i/o port 1 8-bit digit. i/o port 2 8-bit digit. i/o port 3 8-bit digit. i/o xtal1 xtal2 reset ea /v pp ale/prog psen
gms90 series 12 oct. 2000 ver 3.1a cpu the gms90 series is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions are executed in 1.0 m s (40mhz: 300ns). special function register psw reset value of psw is 00 h . bit function cy carry flag ac auxiliary carry flag (for bcd operations) f0 general purpose flag rs1 0 0 1 1 rs0 0 1 0 1 register bank select control bits bank 0 selected, data address 00 h -07 h bank 1 selected, data address 08 h -0f h bank 2 selected, data address 10 h -17 h bank 3 selected, data address 18 h -1f h ov overflow flag f1 general purpose flag p parity flag set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p 76543210 lsb msb bit no. addr. d0 h psw
gms90 series oct. 2000 ver 3.1a 13 special function registers all registers, except the program counter and the four general purpose register banks, reside in the special func- tion register area. the 28 special function registers (sfr) include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. there are also 128 directly addressable bits within the sfr area. all sfrs are listed in table 1, table 1, and table 3. in table 1 they are organized in numeric order of their addresses. in table 2 they are organized in groups which refer to the functional blocks of the gms90 series. table 3 illustrates the contents of the sfrs. table 1. special function registers in numeric order of their addresses address register contents after reset address register contents after reset 80h 81h 82h 83h 84h 85h 86h 87h p0 1) sp dpl dph reserved reserved reserved pcon 1) bit-addressable special function register. ffh 07h 00h 00h xxh 2) xxh 2) xxh 2) 0xx0000 b 2) 2) x means that the value is indetermi nate and the location is reserved. 90h 91h 92h 93h 94h 95h 96h 97h p1 1) reserved reserved reserved reserved reserved reserved reserved ff h 00 h xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) 88h 89h 8ah 8bh 8ch 8dh 8eh 3) 8fh 3) the gms9xx54/56/58 have the auxr0 register at address 8e h . tcon 1) tmod tl0 tl1 th0 th1 + 3) reserved 00h 00h 00h 00h 00h 00h + 3) xxh 2) 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh scon 1) sbuf reserved reserved reserved reserved reserved reserved 00h xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) 8e h reserved xxxxxxx0 b 2) 8e h auxr0 gms9xx51/52 gms9xx54/56/58 xxxxxxxx b 2)
gms90 series 14 oct. 2000 ver 3.1a table 1. special function registers in numeric order of their addresses (contd) address register contents after reset address register contents after reset a0h a1h a2h a3h a4h a5h a6h a7h p2 1) reserved reserved reserved reserved reserved reserved reserved ffh xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) c8h c9h 3) cah cbh cch cdh ceh cfh t2con 1) t2mod rc2l rc2h tl2 th2 reserved reserved 00h + 3) 00h 00h 00h 00h xxh 2) xxh 2) a8h a9h aah abh ach adh aeh afh ie 1) reserved reserved reserved reserved reserved reserved reserved 0x000000b 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) d0h d1h d2h d3h d4h d5h d6h d7h psw 1) reserved reserved reserved reserved reserved reserved reserved 00h xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) b0h b1h b2h b3h b4h b5h b6h b7h p3 1) reserved reserved reserved reserved reserved reserved reserved ffh xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) d8h d9h dah dbh dch ddh deh dfh reserved reserved reserved reserved reserved reserved reserved reserved xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) b8h b9h bah bbh bch bdh beh bfh ip 1) reserved reserved reserved reserved reserved reserved reserved xx000000b 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) e0h e1h e2h e3h e4h e5h e6h e7h acc 1) reserved reserved reserved reserved reserved reserved reserved 00h xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) c0h c1h c2h c3h c4h c5h c6h c7h reserved reserved reserved reserved reserved reserved reserved reserved xx h xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) e8h e9h eah ebh ech edh eeh efh reserved reserved reserved reserved reserved reserved reserved reserved xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2)
gms90 series oct. 2000 ver 3.1a 15 f0h f1h f2h f3h f4h f5h f6h f7h b 1) reserved reserved reserved reserved reserved reserved reserved 00h xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) f8h f9h fah fbh fch fdh feh ffh reserved reserved reserved reserved reserved reserved reserved reserved xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) xxh 2) 1) bit-addressable special function register. 2) x means that the value is indetermi nate and the location is reserved. 3) address c9 h is configured as below. table 1. special function registers in numeric order of their addresses (contd) address register contents after reset address register contents after reset c9 h reserved xxxxxx00 b 2) xxxxxxx0 b 2) c9 h t2mod gms9xx51/52 gms9xx54/56/58
gms90 series 16 oct. 2000 ver 3.1a table 2. special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl psw sp accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer e0h 1) f0h 1) 83h 82h d0h 1) 81h 1) bit-addressable special function register 00h 00h 00h 00h 00h 07h interrupt system ie ip interrupt enable register interrupt priority register a8h 1) b8h 1) 0x000000b 2) xx000000b 2) 2) x means that the value is indetermi nate and the location is reserved ports p0 p1 p2 p3 port 0 port 1 port 2 port 3 80h 1) 90h 1) a0h 1) b0h 1) ffh ffh ffh ffh serial channels pcon 3) sbuf scon 3) this special function register is listed repeatedly since some bit of it also belong to other functional b locks power control register serial channel buffer reg. serial channel 0 control reg. 87h 99h 98h 1) 0xxx0000b 2) xxh 2) 00h timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88h 1) 8ch 8dh 8ah 8bh 89h 00h 00h 00h 00h 00h 00h timer 2 t2con t2mod rc2h rc2l th2 tl2 auxr0 4) 4) the auxr0 is in the gms9xx54/56/58 only. timer 2 control register timer 2 mode register timer 2 reload capture reg., high byte timer 2 reload capture reg., low byte timer 2, high byte timer 2, low byte aux. register 0 c8h 1) c9h cbh cah cdh cch 8eh 00h 00h 00h 00h 00h 00h xxxxxxx0b 2) power saving modes pcon 3) power control register 87h 0xxx0000b 2)
gms90 series oct. 2000 ver 3.1a 17 ? indicates resident in the gms9xx54/56/58, not in 9xx51/52. table 3. contents of sfrs, sfrs in numeric order address register bit76543210 80h p0 81h sp 82h dpl 83h dph 87h pcon smod ---gf1gf0pdeidle 88h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89h tmod gate c/t m1 mt gate c/t m1 m0 8ah tl0 8bh tl1 8ch th0 8dh th1 8eh auxr0 ? ------- a0 ? 90h p1 98h scon sm0 sm1 sm2 ren tb8 rb8 ti ri 99h sbuf a0h p2 a8h ie ea - et2 es et1 ex1 et0 ex0 b0h p3 b8h ip - - pt2 ps pt1 px1 pt0 px0 sfr bit and byte addressable sfr not bit addressable - : this bit location is reserved
gms90 series 18 oct. 2000 ver 3.1a ? indicates resident in the gms9xx54/56/58, not in 9xx51/52. table 3. contents of sfrs, sfrs in numeric order (contd) address register bit76543210 c8h t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c9ht2mod ------ t2oe ? dcen cah rc2l cbh rc2h cch tl2 cdh th2 d0h psw cy ac f0 rs1 rs0 ov f1 p e0h acc f0h b a0 8eh 0 : enable ale signal (generated ale signal) c9h 1 : disable ale signal (not generated ale signal) t2oe 0 : disable timer2 output 1 : enable timer2 output ? ? t2oe : timer2 output enable bit a0 : ale signal disable bit sfr bit and byte addressable sfr not bit addressable - : this bit location is reserved
gms90 series oct. 2000 ver 3.1a 19 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 4: in the "timer" function (c/t = "0") the register is incremented every machine cycle. therefore the count rate is f osc /12. in the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter- nal input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /24. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 2 illustrates the input clock logic. figure 2. timer/counter 0 and 1 input clock logic table 4. timer/counter 0 and 1 operating modes mode description tmod input clock gate c/t m1 m0 internal external (max.) 0 8-bit timer/counter with a divide-by-32 prescaler xx0 0 f osc ? (12 32) f osc ? (24 32) 1 16-bit timer/counter x x 0 1 f osc ? 12 f osc ? 24 2 8-bit timer/counter with 8-bit auto-reload xx1 0 f osc ? 12 f osc ? 24 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops xx1 1 f osc ? 12 f osc ? 24 f osc ? 12 tmod f osc ? 12 p3.4/t0 p3.5/t1 max. f osc /24 c/t =1 3 1 tcon tr0 / 1 tmod gate & p3.2 / int0 p3.3 / int1 timer 0/1 input clock 0 1
gms90 series 20 oct. 2000 ver 3.1a timer 2 timer 2 is a 16-bit timer/counter with an up/down count feature. it can operate either as timer or as an event counter which is selected by bit c/t2 (t2con.1). it has three operating modes as shown in table 5. note: = falling edge table 5. timer/counter 2 operating modes mode t2con t2mo d t2con p1.1/ t2ex remarks input clock rclk or tclk cp/rl2 tr2 dcen exen2 internal external (p1.0/t2) 16-bit auto- reload 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 x x x 0 1 reload upon over- flow reload trigger (fall- ing edge) down counting up counting f osc ? 12 max. f osc ? 24 16-bit capture 0 0 1 1 1 1 x x 0 1 x 16 bit timer/ coun- ter (only up-count- ing) capture th2,tl2 ? rc2h,rc2l f osc ? 12 max. f osc ? 24 baud rate generator 1 1 x x 1 1 x x 0 1 x no overflow interrupt request (tf2) extra external inter- rupt ("timer 2") f osc ? 12 max. f osc ? 24 off x x 0 x x x timer 2 stops - -
gms90 series oct. 2000 ver 3.1a 21 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. the possible baud rates can be calculated using the formulas given in table 7. table 6. usart operating modes mode scon baudrate description sm0 sm1 000 serial data enters and exits through rxd. txd outputs the shift clock. 8-bit are transmit- ted/received (lsb first) 1 0 1 timer 1/2 overflow rate 8-bit uart 10 bits are transmitted (through txd) or received (rxd) 210 or 9-bit uart 11 bits are transmitted (txd) or received (rxd) 3 1 1 timer 1/2 overflow rate 9-bit uart like mode 2 except the variable baud rate table 7. formulas for calculating baud rates baud rate derived from interface mode baudrate oscillator 0 2 timer 1 (16-bit timer) (8-bit timer with 8-bit auto reload) 1,3 1,3 timer 2 1,3 f osc 12 ------------ f osc 32 ------------ f osc 64 ------------ f osc 12 ------------ 2 smod 64 ------------------ f osc 2 smod 32 ------------------ timer 1 overflow () 2 smod 32 ------------------ f osc 12 256 th1 () C [] -------------------------------------------------- f osc 32 65536 rc2h rc2l , () C [] --------------------------------------------------------------------------------- -
gms90 series 22 oct. 2000 ver 3.1a interrupt system the gms90 series provides 5 (4k bytes rom version) or 6 (above 8k bytes rom version) interrupt sources with two priority levels. figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags. figure 3. interrupt request sources pt0 ip.1 pt1 ip.3 pt2 ip.5 ps ip.4 px0 ip.0 px1 ip.2 ea ie.7 et0 ie.1 et1 ie.3 et2 ie.5 es ie.4 ex0 ie.0 ex1 ie.2 tf0 tcon.5 tf1 tcon.7 3 1 tf2 t2con.7 exf2 t2con.6 3 1 ri scon.0 ti scon.1 ie0 tcon.1 ie1 tcon.3 it0 tcon.0 it1 tcon.2 p3.2/ int0 p3.3/ int1 exen2 t2con.3 p1.1/ t2ex timer 2 overflow timer 0 overflow timer 1 overflow : low level triggered : falling edge triggered low priority high priority uart
gms90 series oct. 2000 ver 3.1a 23 a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority in- terrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority level are received simultaneously, the request of higher priority is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which re- quest is serviced. thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9. table 8. interrupt sources and their corresponding interrupt vectors source (request flags) vectors vector address reset ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 reset external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt 0000h 0003h 000bh 0013h 001bh 0023h 002bh table 9. interrupt priority-within-level interrupt source priority external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial channel timer 2 interrupt ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 high low
gms90 series 24 oct. 2000 ver 3.1a power saving modes two power down modes are available, the idle mode and power down mode. the bits pde and idle of the register pcon select the power down mode or the idle mode, respectively. if the power down mode and the idle mode are set at the same time, the power down mode takes precedence. table 10 gives a general overview of the power saving modes. in the power down mode of operation, v cc can be reduced to minimize power consumption. it must be ensured, however, that v cc is not reduced before the power down mode is invoked, and that v cc is restored to its normal operating level, before the power down mode is terminated. the reset signal that terminates the power down mode also restarts the oscillator. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). table 10. power saving modes overview mode entering instruction example leaving by remarks idle mode orl pcon, #01h - enabled interrupt - hardware reset cpu is gated off cpu status registers maintain their data. peripherals are active power-down mode orl pcon, #02h hardware reset oscillator is stopped, contents of on- chip ram and sfrs are maintained (leaving power down mode means redefinition of sfr contents).
gms90 series oct. 2000 ver 3.1a 25 electrical characteristics absolute maximum ratings ambient temperature under bias (t a )...................................................................................... -40 to + 85 c storage temperature (t st )...................................................................................................... -65 to + 150 c voltage on v cc pins with respect to ground (v ss ) ................................................................. -0.5v to 6.5v voltage on any pin with respect to ground (v ss ) ..........................................................-0.5v to v cc +0.5v input current on any pin during overload condition............................................................-15ma to +15ma absolute sum of all input currents during overload condition ...........................................................|100ma| power dissipation ............................................................................................................... .....................1.5w note: stresses above those listed under "absolute maximum ratings" may cause permanent damage of the de- vice. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for longer periods may affect device reliability. during overload conditions (v in >v cc or v in gms90 series 26 oct. 2000 ver 3.1a dc characteristics dc characteristics for gms90c31/32, gms90c51/52/54/56/58 v cc =5v+10%,-15%;v ss =0v; t a =0 cto70 c parameter symbol limit values unit test conditions min. max. input low voltage (except ea , reset) v il -0.5 0.2v cc -0.1 v- input low voltage (ea )v il1 -0.5 0.2v cc -0.3 v- input low voltage (reset) v il2 -0.5 0.2v cc +0.1 v- input high voltage (except xtal1, ea , reset) v ih 0.2v cc +0.9 v cc +0.5 v- input high voltage to xtal1 v ih1 0.7v cc v cc +0.5 v- input high voltage to ea , reset v ih2 0.6v cc v cc +0.5 v- output low voltage (ports 1, 2, 3) v ol -0.45v i ol =1.6ma 1) output low voltage (port0,ale,psen ) v ol1 -0.45v i ol =3.2ma 1) output high voltage (ports 1, 2, 3) v oh 2.4 0.9v cc -v i oh =-80 m a i oh =-10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.4 0.9v cc -v i oh =-800 m a 2) i oh =-80 m a 2) logic 0 input current (ports 1, 2, 3) i il -10 -50 m a v in =0.45v logical 1-to-0 transition cur- rent (ports 1, 2, 3) i tl -65 -650 m a v in =2.0v input leakage current (port 0, ea ) i li - 1 m a 0.45 < v in < v cc pin capacitance c io -10pf f c =1mhz t a =25 c power supply current: active mode, 12mhz 3) idle mode, 12mhz 3) active mode, 24 mhz 3) idle mode, 24mhz 3) active mode, 40 mhz 3) idle mode, 40 mhz 3) power down mode 3) i cc i cc i cc i cc i cc i cc i pd - - - - - - - 21 4.8 36.2 8.2 58.5 12.5 50 ma ma ma ma ma ma m a v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5v 6)
gms90 series oct. 2000 ver 3.1a 27 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 tran- sitions during bus operation. in the worst case (capacitive loading: > 50pf at 3.3v, > 100pf at 5v), the noise pulse on ale line may exceed 0.8v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specifica- tion when the address lines are stabilizing. 3) i cc max at other frequencies is given by: active mode: i cc =1.27 f osc +5.73 idle mode: i cc =0.28 f osc + 1.45 (except otp devices) where f osc is the oscillator frequency in mhz. i cc values are given in ma and measured at v cc =5v. 4) i cc (active mode) is measured with: xtal1 driven with t clch ,t chcl =5ns,v il =v ss +0.5v,v ih =v cc - 0.5v; xtal2 = n.c.; ea = port0 = reset = v cc ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (appr. 1ma). 5) i cc (idle mode) is measured with all output pins disconnected and with all peripherals dis abled; xtal1 driven with t clch ,t chcl =5ns,v il =v ss +0.5v,v ih =v cc - 0.5v; xtal2 = n.c.; reset=ea =v ss ;port0=v cc ; all other pins are disconnected; 6) i pd (power down mode) is measured under following conditions: ea =port0=v cc ; reset = v ss ; xtal2 = n.c.; xtal1 = v ss ; all other pins are disconnected.
gms90 series 28 oct. 2000 ver 3.1a dc characteristics for gms97c51/52/54/56/58 (h) v cc =5v+10%,-15%;v ss =0v; t a =0 cto70 c parameter symbol limit values unit test conditions min. max. input low voltage (except ea , reset) v il -0.5 0.2v cc -0.1 v- input low voltage (ea )v il1 -0.5 0.2v cc -0.3 v- input low voltage (reset) v il2 -0.5 0.2v cc +0.1 v- input high voltage (except xtal1, ea , reset) v ih 0.2v cc +0.9 v cc +0.5 v- input high voltage to xtal1 v ih1 0.7v cc v cc +0.5 v- input high voltage to ea , reset v ih2 0.6v cc v cc +0.5 v- output low voltage (ports 1, 2, 3) v ol -0.45v i ol =1.6ma 1) output low voltage (port0,ale,psen ) v ol1 -0.45v i ol =3.2ma 1) output high voltage (ports 1, 2, 3) v oh 2.4 0.9v cc -v i oh =-80 m a i oh =-10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.4 0.9v cc -v i oh =-800 m a 2) i oh =-80 m a 2) logic 0 input current (ports 1, 2, 3) i il -10 -50 m a v in =0.45v logical 1-to-0 transition cur- rent (ports 1, 2, 3) i tl -65 -650 m a v in =2.0v input leakage current (port 0, ea ) i li - 1 m a 0.45 < v in < v cc pin capacitance c io -10pf f c =1mhz t a =25 c power supply current: active mode, 12mhz 3) idle mode, 12mhz 3) active mode, 24 mhz 3) idle mode, 24mhz 3) active mode, 33 mhz 3) idle mode, 33 mhz 3) power down mode 3) i cc i cc i cc i cc i cc i cc i pd - - - - - - - 21 4.8 36.2 8.2 45 10 50 ma ma ma ma ma ma m a v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5v 4) v cc =5v 5) v cc =5v 6)
gms90 series oct. 2000 ver 3.1a 29 dc characteristics for gms90l31/32, gms90l51/52/54/56/58 v cc = 3.3v + 0.3v, -0.6v; v ss =0v; t a =0 cto70 c parameter symbol limit values unit test conditions min. max. input low voltage v il -0.5 0.8 v - input high voltage v ih 2.0 v cc +0.5 v- output low voltage (ports 1, 2, 3) v ol - 0.45 0.30 v i ol =1.6ma 1) i ol =100 m a 1) output low voltage (port0,ale,psen ) v ol1 - 0.45 0.30 v i ol =3.2ma 1) i ol =200 m a 1) output high voltage (ports 1, 2, 3) v oh 2.0 0.9v cc -v i oh =-20 m a i oh =-10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.0 0.9v cc -v i oh =-800 m a 2) i oh =-80 m a 2) logic 0 input current (ports 1, 2, 3) i il -1 -50 m a v in =0.45v logical 1-to-0 transition cur- rent (ports 1, 2, 3) i tl -25 -250 m a v in =2.0v input leakage current (port 0, ea ) i li - 1 m a 0.45 < v in < v cc pin capacitance c io -10pf f c =1mhz t a =25 c power supply current: active mode, 16 mhz 3) idle mode, 16mhz 3) power down mode 3) i cc i cc i pd - - - 15 5 10 ma ma m a v cc =3.6v 4) v cc =2.6v 5) v cc =2~ 5.5v 6)
gms90 series 30 oct. 2000 ver 3.1a dc characteristics for gms97l51/52/54/56/58 v cc = 3.3v + 0.3v, -0.6v; v ss =0v; t a =0 cto70 c parameter symbol limit values unit test conditions min. max. input low voltage v il -0.5 0.8 v - input high voltage v ih 2.0 v cc +0.5 v- output low voltage (ports 1, 2, 3) v ol - 0.45 0.30 v i ol =1.6ma 1) i ol =100 m a 1) output low voltage (port0,ale,psen ) v ol1 - 0.45 0.30 v i ol =3.2ma 1) i ol =200 m a 1) output high voltage (ports 1, 2, 3) v oh 2.0 0.9v cc -v i oh =-20 m a i oh =-10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.0 0.9v cc -v i oh =-800 m a 2) i oh =-80 m a 2) logic 0 input current (ports 1, 2, 3) i il -1 -50 m a v in =0.45v logical 1-to-0 transition cur- rent (ports 1, 2, 3) i tl -25 -250 m a v in =2.0v input leakage current (port 0, ea ) i li - 1 m a 0.45 < v in < v cc pin capacitance c io -10pf f c =1mhz t a =25 c power supply current: active mode, 12mhz 3) idle mode, 12mhz 3) power down mode 3) i cc i cc i pd - - - 15 5 10 ma ma m a v cc =3.6v 4) v cc =2.6v 5) v cc =2~ 5.5v 6)
gms90 series oct. 2000 ver 3.1a 31 ac characteristics explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stand for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. ac characteristics for gms90 series (12mhz version) external program memory characteristics v cc =5v: v cc =5v + 10%, - 15%; v ss =0v; t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) v cc =3.3v: v cc =3.3v + 0.3v, - 0.6v; v ss =0v; t a =0 cto70 c (c l forport0.aleandpsen outputs = 50pf; c l for all other outputs = 50pf) variable clock : vcc = 5v : 1/t clcl =3.5mhzto12mhz vcc = 3.3v : 1/t clcl =1mhzto12mhz parameter symbol 12 mhz oscillator variable oscillator 1/t clcl =3.5to12mhz unit min. max. min. max. ale pulse width t lhll 127 - 2t clcl -40 - ns address setup to ale t avll 43 - t clcl -40 - ns address hold after ale t llax 30 - t clcl -53 - ns ale low to valid instruction in t lliv -233 -4t clcl -100 ns ale to psen t llpl 58 - t clcl -25 - ns psen pulse width t plph 215 - 3t clcl -35 - ns psen to valid instruction in t pliv -150 -3t clcl -100 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -63 - t clcl -20 ns address valid after psen t pxav ? 75 - t clcl -8 - ns a: address c: clock d: input data h: logic level high i: instruction (program memory contents) l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, t avll = time from address valid to ale low t llpl = time from ale low to psen low
gms90 series 32 oct. 2000 ver 3.1a ? interfacing the gms90 series to devices with float times up to 75 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. address to valid instruction in t aviv -302 -5t clcl -115 ns address float to psen t azpl 0- 0 - ns parameter symbol 12 mhz oscillator variable oscillator 1/t clcl =3.5to12mhz unit min. max. min. max.
gms90 series oct. 2000 ver 3.1a 33 ac characteristics for gms90 series (12mhz) external data memory characteristics advance information (12mhz) external clock drive parameter symbol 12 mhz oscillator variable oscillator 1/t clcl =3.5to12mhz unit min. max. min. max. rd pulse width t rlrh 400 - 6t clcl -100 - ns wr pulse width t wlwh 400 - 6t clcl -100 - ns address hold after ale t llax2 53 - t clcl -30 - ns rd to valid data in t rldv -252 -5t clcl -165 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -97 -2t clcl -70 ns ale to valid data in t lldv -517 -8t clcl -150 ns address to valid data in t avdv -585 -9t clcl -165 ns ale to wr or rd t llwl 200 300 3t clcl -50 3t clcl +50 ns address valid to wr or rd t avwl 203 - 4t clcl -130 - ns wr or rd high to ale high t whlh 43 123 t clcl -40 t clcl +40 ns data valid to wr transition t qvwx 33 - t clcl -50 - ns data setup before wr t qvwh 433 - 7t clcl -150 - ns data hold after wr t whqx 33 - t clcl -50 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 12mhz) unit min. max. oscillator period (v cc =5v) oscillator period (v cc =3.3v) t clcl t clcl 83.3 83.3 285.7 1 ns high time t chcx 20 t clcl -t clcx ns low time t clcx 20 t clcl -t chcx ns rise time t clch -20ns fall time t chcl -20 ns
gms90 series 34 oct. 2000 ver 3.1a ac characteristics for gms90 series (16mhz version) v cc =3.3v+0.3v, - 0.6v; v ss =0v; t a =0 cto70 c (c l for port 0. ale and psen outputs = 50pf; c l for all other outputs = 50pf) external program memory characteristics ? interfacing the gms90 series to devices with float times up to 35 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol 16 mhz oscillator variable oscillator 1/t clcl =3.5to16mhz unit min. max. min. max. ale pulse width t lhll 85 - 2t clcl -40 - ns address setup to ale t avll 23 - t clcl -40 - ns address hold after ale t llax 23 - t clcl -40 - ns ale low to valid instruction in t lliv -150 -4t clcl -100 ns ale to psen t llpl 38 - t clcl -25 - ns psen pulse width t plph 153 - 3t clcl -35 - ns psen to valid instruction in t pliv -88 -3t clcl -100 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -43 - t clcl -20 ns address valid after psen t pxav ? 55 - t clcl -8 - ns address to valid instruction in t aviv -198 -5t clcl -115 ns address float to psen t azpl 0- 0 - ns
gms90 series oct. 2000 ver 3.1a 35 ac characteristics for gms90 series (16mhz) external data memory characteristics advance information (16mhz) external clock drive parameter symbol 16 mhz oscillator variable oscillator 1/t clcl =3.5to16mhz unit min. max. min. max. rd pulse width t rlrh 275 - 6t clcl -100 - ns wr pulse width t wlwh 275 - 6t clcl -100 - ns address hold after ale t llax2 23 - t clcl -40 - ns rd to valid data in t rldv -183 -5t clcl -130 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -75 -2t clcl -50 ns ale to valid data in t lldv -350 -8t clcl -150 ns address to valid data in t avdv -398 -9t clcl -165 ns ale to wr or rd t llwl 138 238 3t clcl - 50 3t clcl +50 ns address valid to wr or rd t avwl 120 - 4t clcl -130 - ns wr or rd high to ale high t whlh 28 97 t clcl - 35 t clcl +35 ns data valid to wr transition t qvwx 13 - t clcl - 50 - ns data setup before wr t qvwh 288 - 7t clcl -150 - ns data hold after wr t whqx 23 - t clcl - 40 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 16mhz) unit min. max. oscillator period t clcl 62.5 285.7 ns high time t chcx 17 t clcl -t clcx ns low time t clcx 17 t clcl -t chcx ns rise time t clch -17ns fall time t chcl -17 ns
gms90 series 36 oct. 2000 ver 3.1a ac characteristics for gms90 series (24mhz version) v cc =5v+10%, - 15%; v ss =0v; t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) external program memory characteristics ? interfacing the gms90 series to devices with float times up to 35 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol 24 mhz oscillator variable oscillator 1/t clcl =3.5to24mhz unit min. max. min. max. ale pulse width t lhll 43 - 2t clcl -40 - ns address setup to ale t avll 17 - t clcl -25 - ns address hold after ale t llax 17 - t clcl -25 - ns ale low to valid instruction in t lliv -80 -4t clcl -87 ns ale to psen t llpl 22 - t clcl -20 - ns psen pulse width t plph 95 - 3t clcl -30 - ns psen to valid instruction in t pliv -60 -3t clcl -65 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -32 - t clcl -10 ns address valid after psen t pxav ? 37 - t clcl -5 - ns address to valid instruction in t aviv -148 - 5t clcl -60 ns address float to psen t azpl 0- 0 - ns
gms90 series oct. 2000 ver 3.1a 37 ac characteristics for gms90 series (24mhz) external data memory characteristics advance information (24mhz) external clock drive parameter symbol 24 mhz oscillator variable oscillator 1/t clcl =3.5to24mhz unit min. max. min. max. rd pulse width t rlrh 180 - 6t clcl -70 - ns wr pulse width t wlwh 180 - 6t clcl -70 - ns address hold after ale t llax2 15 - t clcl -27 - ns rd to valid data in t rldv -118 - 5t clcl -90 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -63 -2t clcl -20 ns ale to valid data in t lldv -200 -8t clcl -133 ns address to valid data in t avdv -220 -9t clcl -155 ns ale to wr or rd t llwl 75 175 3t clcl -50 3t clcl +50 ns address valid to wr or rd t avwl 67 - 4t clcl -97 - ns wr or rd high to ale high t whlh 17 67 t clcl -25 t clcl +25 ns data valid to wr transition t qvwx 5-t clcl -37 - ns data setup before wr t qvwh 170 - 7t clcl -122 - ns data hold after wr t whqx 15 - t clcl -27 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 24mhz) unit min. max. oscillator period t clcl 41.7 285.7 ns high time t chcx 12 t clcl -t clcx ns low time t clcx 12 t clcl -t chcx ns rise time t clch -12ns fall time t chcl -12 ns
gms90 series 38 oct. 2000 ver 3.1a ac characteristics for gms90 series (33mhz version) v cc =5v+10%, - 15%; v ss =0v; t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) external program memory characteristics ? interfacing the gms90 series to devices with float times up to 35 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol 33 mhz oscillator variable oscillator 1/t clcl =3.5to33mhz unit min. max. min. max. ale pulse width t lhll 40 - 2t clcl -20 - ns address setup to ale t avll 10 - t clcl -20 - ns address hold after ale t llax 10 - t clcl -20 - ns ale low to valid instruction in t lliv -56 -4t clcl -65 ns ale to psen t llpl 15 - t clcl -15 - ns psen pulse width t plph 80 - 3t clcl -20 - ns psen to valid instruction in t pliv -35 -3t clcl -55 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -20 - t clcl -10 ns address valid after psen t pxav ? 25 - t clcl -5 - ns address to valid instruction in t aviv -91 -5t clcl -60 ns address float to psen t azpl 0- 0 - ns
gms90 series oct. 2000 ver 3.1a 39 ac characteristics for gms90 series (33mhz) external data memory characteristics advance information (33mhz) external clock drive parameter symbol 33 mhz oscillator variable oscillator 1/t clcl =3.5to33mhz unit min. max. min. max. rd pulse width t rlrh 132 - 6t clcl -50 - ns wr pulse width t wlwh 132 - 6t clcl -50 - ns address hold after ale t llax2 10 - t clcl -20 - ns rd to valid data in t rldv -81 -5t clcl -70 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -46 -2t clcl -15 ns ale to valid data in t lldv -153 - 8t clcl -90 ns address to valid data in t avdv -183 - 9t clcl -90 ns ale to wr or rd t llwl 71 111 3t clcl -20 3t clcl +20 ns address valid to wr or rd t avwl 66 - 4t clcl -55 - ns wr or rd high to ale high t whlh 10 40 t clcl -20 t clcl +20 ns data valid to wr transition t qvwx 5-t clcl -25 - ns data setup before wr t qvwh 142 - 7t clcl -70 - ns data hold after wr t whqx 10 - t clcl -20 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 24mhz) unit min. max. oscillator period t clcl 30.3 285.7 ns high time t chcx 11.5 t clcl -t clcx ns low time t clcx 11.5 t clcl -t chcx ns rise time t clch -5ns fall time t chcl -5 ns
gms90 series 40 oct. 2000 ver 3.1a ac characteristics for gms90 series (40mhz version) v cc =5v+10%, - 15%; v ss =0v; t a =0 cto70 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) external program memory characteristics ? interfacing the gms90 series to devices with float times up to 20 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol 40 mhz oscillator variable oscillator 1/t clcl =3.5to40mhz unit min. max. min. max. ale pulse width t lhll 35 - 2t clcl - 15 - ns address setup to ale t avll 10 - t clcl - 15 - ns address hold after ale t llax 10 - t clcl - 15 - ns ale low to valid instruction in t lliv -55 -4t clcl - 45 ns ale to psen t llpl 10 - t clcl - 15 - ns psen pulse width t plph 60 - 3t clcl - 15 - ns psen to valid instruction in t pliv -25 -3t clcl - 50 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -15 -t clcl - 10 ns address valid after psen t pxav ? 20 - t clcl - 5- ns address to valid instruction in t aviv -65 -5t clcl - 60 ns address float to psen t azpl 5- 5 - ns
gms90 series oct. 2000 ver 3.1a 41 ac characteristics for gms90 series (40mhz) external data memory characteristics advance information (40mhz) external clock drive parameter symbol at 40 mhz clock variable clock 1/t clcl =3.5to40mhz unit min. max. min. max. rd pulse width t rlrh 120 - 6t clcl -30 - ns wr pulse width t wlwh 120 - 6t clcl -30 - ns address hold after ale t llax2 10 - t clcl -15 - ns rd to valid data in t rldv -75 -5t clcl -50 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -38 -2t clcl -12 ns ale to valid data in t lldv -150 - 8t clcl -50 ns address to valid data in t avdv -150 - 9t clcl -75 ns ale to wr or rd t llwl 60 90 3t clcl -15 3t clcl +15 ns address valid to wr or rd t avwl 70 - 4t clcl -30 - ns wr or rd high to ale high t whlh 10 40 t clcl -15 t clcl +15 ns data valid to wr transition t qvwx 5-t clcl -20 - ns data setup before wr t qvwh 125 - 7t clcl -50 - ns data hold after wr t whqx 5-t clcl -20 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 40mhz) unit min. max. oscillator period t clcl 25 285.7 ns high time t chcx 10 t clcl -t clcx ns low time t clcx 10 t clcl -t chcx ns rise time t clch -10ns fall time t chcl -10 ns
gms90 series 42 oct. 2000 ver 3.1a figure 4. external program memory read cycle t lhll t pxav t pxiz t pxix t llax t lliv t pliv t plph t azpl t llpl t avll a0-a7 instr. in a0-a7 a8-a15 a8-a15 t aviv ale psen port 0 port 2
gms90 series oct. 2000 ver 3.1a 43 figure 5. external data memory read cycle figure 6. external data memory write cycle t lhll p2.0-p2.7 or a8-a15 from dph a8-a15 from pch ale psen port 0 port 2 rd t llwl data in a0-a7 from pcl instr. in a0-a7 from t llax2 t avwl t avll t avdv t rlaz t lldv t rlrh t rldv t rhdx t rhdz t whlh ri or dpl t lhll p2.0-p2.7 or a8-a15 from dph a8-a15 from pch ale psen port 0 port 2 wr t llwl data out a0-a7 from pcl instr. in a0-a7 from t llax2 t avwl t avll t wlwh t whqx t whlh ri or dpl t qvwx t qvwh
gms90 series 44 oct. 2000 ver 3.1a figure 7. ac testing: input, output waveforms figure 8. float waveforms figure 9. external clock cycle ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. 0.2v cc + 0.9 0.2v cc - 0.1 test points v cc - 0.5v 0.45v timing measurements are made a v ihmin for a logic 1 and v ilmax for a logic 0. v load + 0.1 v load - 0.1 timing reference points 0.2v cc - 0.1 v oh - 0.1 v ol + 0.1 v load for timing purposes a port pin is no longer floating when a 100mv change from load voltage i ol /i oh 3 20ma. occurs and begins to float when a 100mv change from the loaded v oh /v ol level occurs. t chcl t clch t chcx t clcl t clcx 0.2 v cc - 0.1 0.7 v cc v cc - 0.5v 0.45v
gms90 series oct. 2000 ver 3.1a 45 oscillator circuit figure 10. recommended oscillator circuits oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for ap- propriate values of external components. xtal2 p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 xtal1 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 crystal oscillator mode driving from external source xtal2 p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 xtal1 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 external oscillator signal n.c. c2 c1 c1, c2 = 30pf 10pf for crystals for ceramic resonators, contact resonator manufacturer.
gms90 series 46 oct. 2000 ver 3.1a otp rom verification characteristics rom verification mode 1 figure 11. otp rom verification mode 1 parameter symbol limit values unit min. max. address to valid data t avqv -48t clcl enable to valid data t clcl -48t clcl ns data float after enable t ehqz 048t clcl oscillator frequency 1/t clcl 46mhz address data out p1.0-p1.7 port 0 address: p2.7 p2.0-p2.4 enable t ehqz t elqv t avqv p2.0-p2.5 = a8-a13 data: p1.0-p1.7 = a0-a7 p0.0-p0.7 = d0-d7 input: ale = v ih p2.6-p2.7, psen =v ss ea , reset = v ih2 p3.4 = a14
gms90 series oct. 2000 ver 3.1a 47 eprom characteristics the gms97c5x, 97l5x are programmed by using a modified quick-pulse programming tm algorithm. it dif- fers from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the gms97c5x, 97l5x contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an manufac- tured by hme. table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figure 12 and figure 13. figure 14 show the circuit configuration for normal pro- gram memory verification. reading the signature bytes : the gms97x51/52 signature bytes in locations 030 h and 031 h , the gms97x54/56/58 signature bytes in loca- tions 05e h and 07c h . to read these bytes follow the procedure for eprom verify, except that p3.6 and p3.7 need to be pulled to a logic low. the values are: quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 13. note that the gms97c5x, 97l5x is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 1 and 2, as shown in figure 12. the code byte to be programmed into that location is applied to port 0, rst, psen andpinsofport2and3intable 11 are held at the "program code data" levels indicated in table 11. the ale/prog is pulsed low 25 times(10 times for 97x54/56/58) as shown figure 13. to program the encryption table, repeat the 25 pulses (10 pulses for 97x54/56/58) programming sequence for addresses 0 through 1f h (3f h for 97x54/56/58), using the "program encryption table" levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the security bits, repeat the 25 pulses (10 pulses for 97x54/56/58) programming sequence using the "pgm security bit" levels after one security bit is programmed, further programming of the code memory and device location contents remarks gms97x51 30 h 31 h e0 h 73 h manufacturer id device id gms97x52 30 h 31 h e0 h 71 h manufacturer id device id gms97x54 5e h 7c h e0 h 54 h manufacturer id device id gms97x56 5e h 7c h e0 h 56 h manufacturer id device id gms97x58 5e h 7c h e0 h 58 h manufacturer id device id
gms90 series 48 oct. 2000 ver 3.1a encryption table is disabled. however, the other security bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free glitches and overshoot. figure 12. programming configuration program verification if security bit 2 has not been programmed, the on-chip program memory can be read out for program verifica- tion. the address of the program memory location to be read is applied to ports 1 and 2 as shown in figure 15. the other pins are held at the "verify code data" levels indicated in table 11. the contents of the address lo- cation will be emitted on port 0 for this operation. if the encryption table has been programmed, the data pre- sented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0 -p2.5 a0-a7 1 1 1 4~6mhz 1 1 0 gms97x51/52: +12.75v gms97x54/56/58: 100 m s 25 pulses to gnd 100 m s 10 pulses to gnd + note note: program data a8-a13 +5v p3.4 a14
gms90 series oct. 2000 ver 3.1a 49 program memory lock bits the two-level program lock system consists of 2 lock bits and a 32-byte (64-byte for gms97x54/ 56/58) encryption array which are used to protect the program memory against software piracy. encryption array: within the eprom array are 32 bytes (64 bytes for gms97x54/56/58) of encryption array that are initially unprogrammed (all 1s). every time that a byte is addressed during a verify, address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified form, it is recommended that whenever the encryption array is used, at least one of the lock bits be pro- grammed as well. program / verify algorithms any algorithm in agreement with the conditions listed in table 11, and which satisfies the timing specifications is suitable. notes: 1. 0 = valid low for that pin, "1" = valid high for that pin. 2. v pp =12.75v 0.25v 3. v cc =5v 10% during programming and verification. 4. ale/prog receives 25 (10 for gms97x54/56/58) programming pulses while v pp is held at 12.75v. each programming pulse is low for 100us ( 10us) and high for a minimum of 10 m s. table 11. eprom programming modes mode rst psen ale/ prog ea / v pp p2.7 p2.6 p3.7 p3.6 readsignature 10110000 program code data 100v pp 1011 verify code data 10110011 program encryption table 100v pp 1010 program security bit 1 100v pp 1111 program security bit 2 100v pp 1100 lock bit protection modes u: unprogrammed, p: programmed mode lb1 lb2 protection type 1 u u no program lock features 2 p u further programming of the eprom is disabled 3 p p sameasmode2,alsoverifyis disabled
gms90 series 50 oct. 2000 ver 3.1a figure 13. prog waveform figure 14. program verification 100 m s 10 min. 10 m s 100 m s 10 in the gms97x51/52 ale/prog in the gms97x54/56/58 ale/prog 25 pulses 10 pulses enlarged view p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0 -p2.5 a0-a7 1 1 1 4~6mhz 1 0 0 1 1 program data a8-a13 +5v p3.4 a14 10k w
gms90 series oct. 2000 ver 3.1a 51 eprom programming and verification characteristics t a =21 cto27 c, v cc =5v+10%, - 15%; v ss =0v; figure 15. eprom programming and verification parameter symbol limit values unit min. max. programming supply voltage v pp 12.5 13.0 v programming supply current i pp -50ma oscillator frequency 1/t clcl 46mhz address setup to prog low t avgl 48t clcl -- address hold after prog t ghax 48t clcl -- data setup to prog t dvgl 48t clcl -- data hold after prog t ghdx 48t clcl -- p2.7 (enable )hightov pp t ehsh 48t clcl -- v pp setup to prog t shgl 10 - m s v pp hold after prog t ghsl 10 - m s prog width t glgl 90 110 m s address to data valid t avqv -48t clcl - enable low to data valid t elqv -48t clcl - data float after enable t ehqz 048t clcl - prog high to prog low t ghgl 10 - m s address address p1.0-p1.7 p2.0-p2.5 p3.4 data in data out port 0 ale/prog ea /v pp p2.7 t ghsl t ghgl t avgl t ghax t ghdx t ehsh t shgl t dvgl 25 or 10 pulses t glgl t avqv t elqv t ehqz ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ v pp ttl high programming verification (enable ) ttl high ttl high
gms90 series 52 oct. 2000 ver 3.1a plastic package p-lcc-44 (plastic leaded chip-carrier) 0.180 0.165 unit: inch 44plcc 0.012 0.0075 0.120 0.090 0.032 0.026 0.630 0.590 min. 0.020 0.656 0.650 0.695 0.685 0.656 0.650 0.695 0.685 0.050 bsc 0.021 0.013
gms90 series oct. 2000 ver 3.1a 53 plastic package p-dip-40 (plastic dual in-line package) unit: inch 2.075 2.045 0.200 max. 0.022 0.015 0.065 0.045 0.100 bsc 0.550 0.530 0.600 bsc 0-15 0 . 0 1 2 0 . 0 0 8 40dip 0.140 0.120 min. 0.015
gms90 series 54 oct. 2000 ver 3.1a plastic package p-mpqf-44 (plastic metric quad flat package) 2.35 max. see detail "a" 1.03 0.73 0-7 0.25 0.10 1.60 ref detail "a" unit: mm 0.45 0.30 0.80 bsc 2.10 1.95 44mqfp 0 . 1 3 0 . 2 3 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95
mask order & verification sheet gms90x5x-gb 1. customer information company name 2. device information 3. marking specification 4. delivery schedule customer sample date risk order yyyy mm dd quantity hynix confirmation application order date yyyy mm dd te l : fax: name & signature: package hynix yyww korea 5. rom code verification verification date: yyyy mm dd approval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to make mask set. check sum: te l : fax: name & signature: te l : fax: name & signature: mask data hitel chollian internet file name: ( .hex) (please check mark into ) hynix semiconductor pcs check sum: customer should write inside thick line box. this box is written after 5.verification. rom size 4k vol./freq. gms90 -gb ? siemens 92 5 customers part number without hynix yyww korea 90 -gb ? siemens 92 5 40pdip or 44plcc 44mqfp c: 5v l: 3v rom size 1: 4k 2: 8k 4: 16k 6: 24k 8: 32k yyyy mm dd pcs 8k 16k 24k 32k 44mqfp 44plcc 40pdip 12mhz 24mhz 40mhz 12mhz 16mhz 5v 3v normal super rom: 16,24,32k rom: 4k,8k rom protection

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